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Transactional memory
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#	Item
81	Understanding Hardware Transactional Memory Gil Tene, CTO & co-Founder, Azul Systems @giltene Add to Reading List Source URL: qconlondon.com Language: English - Date: 2016-04-05 11:46:51
82	Performance Evaluation of Adaptivity in STM Mathias Payer and Thomas R. Gross Department of Computer Science, ETH Zürich Add to Reading List Source URL: hexhive.github.io Language: English - Date: 2016-06-13 11:08:40 Computing Concurrency control Transaction processing Data management Software Software transactional memory Synchronization Lock Transactional memory File locking
83	Using Hardware Transactional Memory to Enable Speculative Trace Optimization Juan Salamanca Jos´e Nelson Amaral Add to Reading List Source URL: www.researchgate.net Language: English
84	StackTrack: An Automated Transactional Approach to Concurrent Memory Reclamation Dan Alistarh ∗ MSR Cambridge Add to Reading List Source URL: research.microsoft.com Language: English - Date: 2014-04-02 06:04:45
85	Appears in the proceedings of the 34th International Symposium on Microarchitecture (MICRO), Dec. 3-Dec. 5, 2001, Austin, Texas. Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution Ravi Rajwar a Add to Reading List Source URL: pages.cs.wisc.edu Language: English - Date: 2001-10-10 12:33:46 Concurrency control Computing Computer architecture Test-and-set Transactional memory Non-blocking algorithm Synchronization Monitor Lock Linearizability Consistency model CPU cache
86	Understanding Transactional Memory Performance Donald E. Porter and Emmett Witchel The University of Texas at Austin {porterde,witchel}@cs.utexas.edu Abstract—Transactional memory promises to generalize transactional p Add to Reading List Source URL: www3.cs.stonybrook.edu Language: English - Date: 2010-08-31 00:38:57 Computing Concurrency control Transaction processing Data management Transactional memory Parallel computing Computer memory Software transactional memory Rock Benchmark Lock Linearizability
87	Reduced Hardware Transactions: A New Approach to Hybrid Transactional Memory Alexander Matveev Nir Shavit Add to Reading List Source URL: mcg.cs.tau.ac.il Language: English - Date: 2013-03-18 08:28:41
88	Reduced Hardware Transactions: A New Approach to Hybrid Transactional Memory Alexander Matveev Nir Shavit Add to Reading List Source URL: mcg.cs.tau.ac.il Language: English - Date: 2013-09-08 03:50:53
89	Technical Report UCAM-CL-TR-579 ISSNNumber 579 Add to Reading List Source URL: www.cl.cam.ac.uk Language: English - Date: 2004-02-13 14:20:06 Concurrency control Computing Data management Computer architecture Non-blocking algorithm Lock Mutual exclusion Linearizability Readerswriter lock Synchronization Software transactional memory Memory barrier
90	Performance Evaluation of Adaptivity in Software Transactional Memory Mathias Payer ETH Zurich, Switzerland Abstract—Transactional memory (TM) is an attractive platform for parallel programs, Add to Reading List Source URL: www.nebelwelt.net Language: English - Date: 2016-04-13 09:07:44